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INTEGRATED CIRCUITS
DATA SHEET
TDA8050A QPSK transmitter
Product specification File under Integrated Circuits, IC02 1999 Nov 05
Philips Semiconductors
Product specification
QPSK transmitter
FEATURES * Programmable gain * PLL controlled carrier frequency * 3-wire transmission bus * 5 V supply voltage. APPLICATIONS * QPSK modulation. GENERAL DESCRIPTION The Quadrature Phase Shift Keying (QPSK) transmitter IC is a monolithic bipolar IC dedicated to quadrature modulation of the I and Q signals. It includes: * Two double balanced mixers * A balanced voltage controlled oscillator (VCO) with 0 to 90 degrees signal generation for modulation * A phase locked loop (PLL) for IF frequency control * A conversion mixer * A PLL for RF frequency control * A gain controlled output amplifier * A 3-wire bus and an output buffer. QUICK REFERENCE DATA SYMBOL VCC fc Vo(max) fxtal fref(MOD) fstep Tamb supply voltage output centre frequency maximum output level crystal frequency reference frequency for modulator synthesizer frequency step size for converter synthesizer ambient temperature PARAMETER MIN. 4.75 5 - 1 - 100 0
TDA8050A
Two PLLs are incorporated, the first PLL includes: * A fixed main divider * A crystal oscillator and its programmable reference divider * A phase/frequency detector, combined with a fixed charge pump. The second PLL includes: * A divide-by-four preamplifier * A 12-bit programmable divider * A crystal oscillator and its programmable reference divider * A phase/frequency detector, combined with a programmable charge pump which drives the tuning amplifier, including 30 V output.
TYP. 5.00 - 55 - 250 - -
MAX. 5.25 65 - 4 - 500 70
UNIT V MHz dBmV MHz kHz kHz C
ORDERING INFORMATION TYPE NUMBER TDA8050A PACKAGE NAME SO32 DESCRIPTION plastic small outline package; 32 leads; body width 7.5 mm VERSION SOT287-1
1999 Nov 05
2
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IF_FILTC AVCC1 26 AGND1 9 IF_FILT 24 25 RF_OUTC RF_INC SW_CAP 32 AVCC2 29 AGND2 4 RF_OUT RF_IN 28 27 30 31
BLOCK DIAGRAM
Philips Semiconductors
QPSK transmitter
MODULATOR
I_IN I_INC 5 6
CONVERTER
x
1
OUTEN BUF_OUTC BUF_OUT
Q_IN Q_INC DVCC DGND CLK DATA EN LOCK
7 8 13 18 14 15 16 23 3-WIRE BUS TRANCEIVER 90 1/2
x
3 2
x
0 DAC
3
TDA8050A
CHARGE PUMP
DIGITAL PHASE COMPARATOR
FIXED MAIN DIVIDER
PROGRAMMABLE MAIN DIVIDER
PROGRAMMABLE REF DIVIDER
PROGRAMMABLE REF DIVIDER
DIGITAL PHASE COMPARATOR
PROGRAMMABLE CHARGE PUMP
12
10 TKAMOD
11
17 OSC_IN
22
21
20
19
FCE433
CP_MOD
TKBCONV TKACONV
TUNECONV
CP_CONV
TKBMOD
Product specification
TDA8050A
Fig.1 Block diagram.
Philips Semiconductors
Product specification
QPSK transmitter
PINNING SYMBOL OUTEN BUF_OUT BUF_OUTC AGND2 I_IN I_INC Q_IN Q_INC AGND1 TKA_MOD TKB_MOD CP_MOD VCCD CLK DATA EN OSC_IN DGND CP_CONV TUNE_CONV TKB_CONV TKA_CONV LOCK IF_FILT IF_FILTC VCCA1 RF_OUTC RF_OUT VCCA2 RF_IN RF_INC SW_CAP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 output enable output amplifier balanced output output amplifier balanced output converter analog ground 2 I balanced input I balanced input Q balanced input Q balanced input modulator analog ground 1 modulator VCO tank circuit input 2 modulator VCO tank circuit input 1 modulator charge pump output for PLL loop filter digital supply voltage 3-wire bus serial control clock 3-wire bus serial control data 3-wire bus serial control enable crystal oscillator input digital ground converter charge pump output for PLL loop filter tuning voltage output for converter VCO converter VCO tank circuit input 1 converter VCO tank circuit input 2 lock detect signal IF balanced output to filter IF balanced output to filter modulator analog supply voltage RF balanced output to filter RF balanced output to filter converter analog supply voltage RF balanced input to programmable amplifier RF balanced input to programmable amplifier switch capacitor DESCRIPTION
TDA8050A
1999 Nov 05
4
Philips Semiconductors
Product specification
QPSK transmitter
FUNCTIONAL DESCRIPTION
TDA8050A
The I and Q signals are balanced analog signals of 400 mV (p-p). These are mixed by two double balanced mixers with the output signal generated by a first local oscillator, to provide the modulated signal. The modulated signal is then filtered by an IF filter. This filtered signal, together a signal generated by a second local oscillator, is converted by a balanced mixer to produce the QPSK signal. The QPSK signal is amplified by a gain controlled output amplifier to a level suitable for transmission. The gain of the amplifier is bus controlled and this amplifier can be disabled when not transmitting, to provide signal attenuation. The amplified signal is applied to an on-chip amplifier with two balanced outputs (open collector) connected to two off-chip resistors (values 150 ), in turn connected to 9 V. The balanced outputs drive a 2 : 1 transformer (Siemens V944) loaded with 75 , which gives an output level of 55 dBmV. The output frequency range of the transmitter is 5 to 65 MHz. The frequency of the first local oscillator operates at twice the frequency (i.e. 280 MHz), fixed by a PLL implemented in the circuit. The frequency of the second local oscillator operates in the 145 to 205 MHz bandwidth and can be programmed through the PLL implemented in the circuit. The VCOs of both the first and second local oscillators need an external LC tank circuit with two varicap diodes. The data sent to the PLL is loaded in bursts framed by signal EN. Programming rising clock edges and their appropriate data bits are ignored until EN goes active (LOW). The internal latches are updated with the latest programming data when EN returns to inactive (HIGH). Only the last 14 bits are stored in the programming register. No check is made on the number of clock pulses received during the time that programming is enabled. If EN goes high while CLK is still LOW, a wrong active clock edge will be generated, causing a shift of the data bits. At power up, EN should be HIGH. The lock detector output LOCK is HIGH when both PLLs are in lock. The main divider ratio and the reference divider ratios are provided via the serial bus. A control register controls the Digital-to-Analog-Converter (DAC), the output amplifier and the charge pump currents (see Tables 1, 2 and 3). Fig.2 Pin configuration.
OUTEN 1 BUF_OUT 2 BUF_OUTC 3 AGND2 4 I_IN 5 I_INC 6 Q_IN 7 Q_INC 8
32 SW_CAP 31 RF_INC 30 RF_IN 29 AVCC2 28 RF_OUT 27 RF_OUTC 26 AVCC1 25 IF_FILTC
TDA8050A
AGND1 9 TKAMOD 10 TKBMOD 11 CP_MOD 12 DVCC 13 CLK 14 DATA 15 EN 16
FCE434
24 IF_FILT 23 LOCK 22 TKACONV 21 TKBCONV 20 TUNECONV 19 CP_CONV 18 DGND 17 OSC_IN
1999 Nov 05
5
Philips Semiconductors
Product specification
QPSK transmitter
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC tsc VMAX Vo(tune) VO(buf) Ptot Tamb Tstg Tj(max) HANDLING Human Body Model (HBM): The IC pins withstand 2 KV, except pins 27 and 28 (1750 V). Machine Model (MM): The IC pins withstand 100 V. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS supply voltage short-circuit time (every pin to VCC or GND) voltage on all pins except BUF_OUT, BUF_OUTC and TUNE_CONV output tuning voltage output buffer voltage on pins BUF_OUT and BUF_OUTC maximum power dissipation ambient temperature storage temperature maximum junction temperature PARAMETER - -0.3 -0.3 - - 0 -40 - MIN. -0.3
TDA8050A
MAX. +6.0 10 VCC +30 10 940 70 +150 150 s
UNIT V V V V mW C C C
VALUE 63
UNIT K/W
thermal resistance from junction to ambient in free air
CHARACTERISTICS Measured in application circuit with the following conditions; VCC = 5 V, Tamb = 25 C; all AC units are RMS values, unless otherwise specified. SYMBOL Supply VCCA1 ICCA1 VCCA2 ICCA2 ICC(buf) VCCD ICCD VCC(tune) modulator analog supply voltage modulator analog supply current converter analog supply voltage converter analog supply current buffer output supply current digital supply voltage digital supply current tuning supply voltage 4.75 33 4.75 39 39 4.75 20.5 - 5 39 5 47 43 5 23.5 - 5.25 45 5.25 55 47 5.25 26.5 30 V mA V mA mA V mA V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Quadrature modulator I and Q inputs Vi(DC) Vi(p-p) fi(max) Zi(dif) B(1 dB) Modulator fc A LO(sup) Zo(dif) FOSC(mod) VO VO fc Zo(dif) IP3 H2 H3 SO output centre frequency amplitude imbalance phase imbalance LO suppression differential output impedance see Fig.3 see Fig.3 - - - - - - f = 5 MHz; Vi = 100 mVdif at I and Q inputs f = 5 to 65 MHz; Vi = 100 mVdif at I and Q inputs 37.5 - 5 - see Fig.4 f = 10 to 130 MHz; Vi = 100 mVdif at I and Q inputs f = 15 to 195 MHz; Vi = 100 mVdif at I and Q inputs f = 5 to 65 MHz; Vi = 100 mVdif at I and Q inputs - - - - - - - -28 1.8 - 40 - - 150 - - - - 140 1 2 - - 280 MHz dB deg dBc k input DC level signal input level (balanced) (peak-to-peak) I and Q maximum input frequency differential input impedance 1 dB bandwidth amplifier indicative indicative indicative - - - - - 0.5 x VCC - 400 10 4.4 10 500 - - - V mV MHz k MHz
Modulator VCO oscillation frequency MHz
Converter output output level output flatness output centre frequency differential output impedance 3rd order interception point at I input 2nd order harmonic of 5 to 65 MHz signal 3rd order harmonic of 5 to 65 MHz signal mixer spurious outputs of 5 to 65 MHz signal 42.5 2 65 - 52 -40 -40 -45 dBmV dB MHz dBmV dBc dBc dBc
Converter VCO fosc(min) fosc(max) minimum oscillation frequency maximum oscillation frequency - 205 - - 145 - MHz MHz
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
SYMBOL
PARAMETER
CONDITIONS
MIN. - -
TYP.
MAX. - 2 -
UNIT
Programmable gain and output buffer; note 1 Zi(dif) G bufO differential input impedance output level step size output level adjust range Vi = 30 dBmV sine wave 65 MHz at pins RF_IN and RF_INC; DAC = 0 to 31 f = 5 to 65 MHz; Vi = 30 dBmV sine wave; DAC = 28 output buffer on output buffer off Vi = 100 mVdif; DAC = 28; f = 65 MHz; OE = 0,5 V see Fig.5 see Fig.5 f = 10 to 65 MHz; see Fig.6 f = 65 to 120 MHz; see Fig.6 f = 15 to 65 MHz; see Fig.6 f = 65 to 120 MHz; see Fig.6 5.6 - 39 k dB dB
32
Vo Vo VIL(ENL) VIH(ENH) ISO GV(max) Vo(1dB) H2 H3
operational output level output flatness output controlled enable low output controlled enable high disable isolation maximum gain 1 dB compression point 2nd order harmonic of 5 to 65 MHz signal 3rd order harmonic of 5 to 65 MHz signal
- - - 2.4 -35 17 58 - - - - - - -
55 3 - - -90 18.5 - - - - - -75 -95 -
- 5 0.8 - - - - -45 -35 -45 -35 - - -40
dBmV dB V V dBc dB dBmV dBc dBc dBc dBc
Overall; note 1 osc H2 phase noise 2nd order harmonic of 5 to 65 MHz signal 3rd order harmonic of 5 to 65 MHz signal at 10 kHz; note 2 at 100 kHz; note 2 f = 10 to 130 MHz; Vin = 100 mVdif at I and Q inputs; Vout = 55 dBmV f = 15 to 195 MHz; Vin = 100 mVdif at I and Q inputs; Vout = 55 dBmV dBc/Hz dBc/Hz dBc
H3
-
-
-40
dBc
So
spurious signals of 5 to 65 MHz f = 5 to 65 MHz; Vin = 100 mVdif signal at I and Q inputs; Vout = 55 dBmV 3rd order interception point at I input total isolation at I/Q midrange carrier to noise ratio at final output at 2 MHz from carrier see Fig.7 Vin = 100 mVdif; Vout = 35 to 55 dBmV; f = 65 MHz
-
-
-45
dBc
IP3 ISOtot C/N
- - -
- -90 113
49 -65 -
dBmV dBc dBc/Hz
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
SYMBOL Crystal oscillator fxtal Zi Vi(DC) fref(mod) RDR1 ND1 I(cp) fstep RD2 RDR2 ND2 NDR2 3-wire bus VIL VIH VO(lock) VO(unlock) fclk tsu th(CLK) td(strt) td(stp) Notes
PARAMETER
CONDITIONS
MIN. -
TYP.
MAX.
UNIT
crystal frequency input impedance DC input level
note 3 fxtal = 4 MHz
1 600 - - 4 -
4 - - - 16 - - 500 - 160 - 1800
MHz V
1200 2.9
Modulator synthesizer reference frequency programmable reference divider ratio fix main divider ratio charge-pump current fixed 250 - 1120 0.30 - 2 - 4 - kHz
- 100 - 4 -
mA
Converter synthesizer step size fix reference divider ratio programmable reference divider see Tables 4 and 5 ratio fix main divider ratio programmable main divider ratio see Tables 4 and 5 kHz
290
input LOW level input HIGH level
- 2.4 - - - see Fig.8 see Fig.8 see Fig.8 see Fig.8 - - - -
- - 5 0.02
0.8 - - - - - - - -
V V
Lock detect pin output voltage (LOCK) output voltage (UNLOCK) V V
Serial control clock clock frequency input data to CLK set-up time input data to CLK hold time delay to rising clock edge delay from last clock edge 330 2 1 3 3 kHz s s s s
1. All specification points of the output section and the overall circuit are measured after the 2 : 1 transformer (Siemens V944) loaded with 75 . 2. Overall phase noise: a) Converter: I(cp) = 0.36 mA; fref = 25 kHz. b) I and Q = 100 mVdif. c) DAC = 28. d) f = 65 MHz. 3. The crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is serial resonant with a load capacitance of 18 to 20 pF. The connection to VCC is preferred but it might also be to GND. 1999 Nov 05 9
Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
FCE435
IF_FILT imbalance LO(sup)
measure 2 f lo(2)
measure 1 f lo(2) frequency
The amplitude imbalance and the LO suppression are measured in the spectrum of the signal measured at the output IF_FILT and are defined in the following conditions: measure 1: I input frequency = 500 kHz; I input level = 400 mV (p-p) sine wave; unused input as 0 V differential. measure 2: Q input frequency = 500 kHz; Q input level = 400 mV (p-p) sine wave; unused input as 0 V differential.
Fig.3 Imbalance and LO suppression.
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
handbook, full pagewidth
I_IN 50 50 500 kHz 300 kHz I_INC Q_IN Q_INC
RF_OUT RF_OUTC
SPECTRUM ANALYZER
IM3
64.1
64.5
64.7
65
40
65.1
65.3
65.5 65.7 f (MHz)
FCE436
f1 = 300 kHz, f2 = 500 kHz and frf = 65 MHz.
Fig.4 IP3 set-up measurement.
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
handbook, full pagewidth
Siemens V944 50 RF_IN RF_INC BUF_OUTC 150 BUF_OUT 150 9V
75 /50 ADAPTER
SPECTRUM ANALYZER
gain (dB) Gmax Gmax - 1
Vo(-1 dB)
Vo
FCE437
DAC = 31. f = 65 MHz. Vi variable to have a variable output voltage.
Fig.5 Maximum gain and compression point.
handbook, full pagewidth
Siemens V944 RF_IN RF_INC BUF_OUTC 150 BUF_OUT 150 9V
75 /50 ADAPTER
SPECTRUM ANALYZER
FCE438
DAC = 28. f = 5 to 65 MHz. Vi such that Vo = 55 dBmV (rms) at 5 MHz.
Fig.6 Harmonics of output sections H2 and H3.
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
handbook, full pagewidth
OUTEN = 0 V BUF_OUT 150
Siemens V944 I_IN
75 /50 ADAPTER
SPECTRUM ANALYZER
Vi(dif) = 100 mVdif
I_INC BUF_OUTC Q_IN 150
9V
Vi(dif) = 100 mVdif
Q_INC
DAC = 28
OUTEN = 5 V BUF_OUT 150
Siemens V944 I_IN
75 /50 ADAPTER
SPECTRUM ANALYZER
0V I_INC BUF_OUTC Q_IN 0V Q_INC DAC = 28 150
9V
FCE439
ISOtot = Vout1(dB) - Vout2(dB). frf = 65 MHz.
Fig.7 Total isolation (ISOtot).
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
APPLICATION INFORMATION
TDA8050A
t su
t h(CLK)
T cy
CLK
DATA
EN
t d(strt)
t d(stp)
FCE440
Fig.8 3-wire bus timing.
Table 1
Data format; note 1 DATA ADDRESS D4 D3 D2 D1 D0 AD1 AD0 last in
D11 D10 first in
D9
D8
D7
D6
D5
Modulator reference divider ratio X X
Converter reference divider ratio R6 R5 R4 R3 R2 R1 R0 0 1
MP1(2) MP0(2) R7
Control register X X X OEN(3) CR2(4) CR1 CR0(4) DAC4(5) DAC3 DAC2 DAC1 DAC0 1 0
Main divider ratio P11 Notes 1. X = don't care. 2. MP1 and MPO: modulator reference divider ratio (see Table 2). 3. When OEN (output enable) is at logic 0, output is disabled; at logic 1, output is enabled. 4. CR2 and CRO: converter synthesizer charge pump current (see Table 3). 5. When DAC4 to DAC0 is at logic 0, minimum gain is programmed; at logic 1, maximum gain is programmed. P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 1
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
Table 2 Modulator reference divider ratio MP1 1 1 0 Table 3 MP0 1 0 1
TDA8050A
PROGRAMMED RATIO 4 8 16
Converter synthesizer charge pump current CR2 0 0 0 0 0 0 1 CR1 0 0 0 0 1 1 0 CR0 0 0 1 1 0 1 0 LOCK_CONV(1) 0 1 0 1 X X X ICP(mA) 1.2 0.36 0.36 0.1 0.1 0.36 1.2
Note 1. LOCK_CONV is an internal signal. When at logic 0, converter PLL is out-of-lock. When at logic 1, converter PLL is in-lock. Table 4 Converter synthesizer fcomp = fosc/RD. fosc\fcomp 1 MHz 4 MHz 25 kHz 40 160 50 kHz 20 80 125 kHz 8 32
Table 5 Converter synthesizer; ND = 4 f_lo = ND x NDR x fcomp = NDR x step. flo\step 145 MHz 205 MHz 100 kHz 1450 2050 200 kHz 725 1025 500 kHz 290 410
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
handbook, full pagewidth
+5 V Siemens V944 150 +9 V 150
OUTEN
1
32
SW_CAP
BUF_OUT
2
31
RF_INC 100 nF 680
BUF_OUTC
3
30
RF_IN 100 nF 47 pF 390 nH 390 nH
AGND2
4
29
AVCC2
+5 V
100 nF
I_IN
5
28
RF_OUT 100 nF 27 pF
100 100 nF I_INC 6 27 RF_OUTC
100 nF 100 nF Q_IN AVCC1 +5 V
7
26
100 100 nF Q_INC 8 25 IF_FILTC 68 nH 24 IF_FILT 140 MHz TKAMOD LOCK BB132 10 k (2x) 11 22 TKACONV 56 nH CP_MOD 10 k 8.2 nF DVCC 13 20 TUNECONV 10 k 330 pF CLK 14 19 CP_CONV +30 V 100 nF 10 nF 27 k 12 21 TKBCONV 39 pF 4.7pF 39 pF 22 k 820 pF 18 pF
TDA8050A
AGND1 10 k BB133 (2x) 15 pF 22 k 10 pF 10 23 9
22 nH TKBMOD
22 k
10 k 15 pF 22 k 330 pF 330 pF
10 k
22 k
DATA
15
18
DGND
EN
16
17
OSC_IN
4 MHz
FCE441
Fig.9 Application diagram.
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
INTERNAL PIN CONFIGURATION SYMBOL OUTEN SW_CAP PIN 1 32 DESCRIPTION
TDA8050A
DC VOLTAGE n.a. 1.7 V
1
32
FCE442
BUF_OUT BUF_OUTC
2 3
2 3
5.8 V 5.8 V
FCE443
AGND2
4
4
0
FCE444
I_IN I_INC
5 6
5 6
2.5 V 2.5 V
FCE445
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
SYMBOL Q_IN Q_INC
PIN 7 8
7
DESCRIPTION
DC VOLTAGE 2.5 V 2.5 V
8
FCE446
AGND1
9
9
0
FCE447
TKA_MOD TKB_MOD
10 11
3.1 V 3.1 V
10
FCE448
11
CP_MOD
12
2.1 V
12
FCE449
VCCD
13
supply voltage
5V
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
SYMBOL CLK
PIN 14
DESCRIPTION
DC VOLTAGE n.a.
14
FCE450
DATA
15
n.a.
15
FCE451
EN
16
n.a.
16
FCE452
OSC_IN
17
2.9 V
VCC
17
FCE453
DGND
18
0V
18
FCE454
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
SYMBOL CP_CONV
PIN 19
DESCRIPTION
VCC
DC VOLTAGE 2.1 V
down
19 up
FCE455
TUNE_CONV
20
20
VVT
FCE456
TKB_CONV TKA_CONV
21 22
3.1 V 3.1 V
21
FCE457
22
LOCK
23
0V 5V
23
FCE458
1999 Nov 05
20
Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
SYMBOL IF_FILT IF_FILTC
PIN 24 25
DESCRIPTION
DC VOLTAGE 2.1 V 2.1 V
24
25
FCE459
VCCA1 RF_OUTC RF_OUT
26 27 28
supply voltage
5V 3.7 V 3.7 V
27
28
FCE460
VCCA2 RF_IN RF_INC
29 30 31
supply voltage
5V 2.1 V 2.1 V
30
31
FCE461
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
PACKAGE OUTLINE SO32: plastic small outline package; 32 leads; body width 7.5 mm
TDA8050A
SOT287-1
D
E
A X
c y HE vM A
Z 32 17
Q A2 A1 pin 1 index Lp 1 e bp 16 wM L detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 0.02 0.01 c 0.27 0.18 0.011 0.007 D (1) 20.7 20.3 0.81 0.80 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.419 0.394 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.2 1.0 0.047 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.95 0.55 0.037 0.022
0.012 0.096 0.004 0.086
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-25 97-05-22
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA8050A
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Nov 05
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Philips Semiconductors
Product specification
QPSK transmitter
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable
TDA8050A
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 Nov 05
24
Philips Semiconductors
Product specification
QPSK transmitter
NOTES
TDA8050A
1999 Nov 05
25
Philips Semiconductors
Product specification
QPSK transmitter
NOTES
TDA8050A
1999 Nov 05
26
Philips Semiconductors
Product specification
QPSK transmitter
NOTES
TDA8050A
1999 Nov 05
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/25/01/pp28
Date of release: 1999
Nov 05
Document order number:
9397 750 06123

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